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The object of the present invention is a method for calibrating the offset of comparators senal digital pseudoaleatoria analog to digital converters ADCs. Application to a direct conversion topology known as type ADC fl ash allows concurrent calibration of nonlinearity due to said offset. Among these architectures the sigma-delta topologies, subranging, interpolation of successive approximations, interleaved and senal digital pseudoaleatoria also known as Pipeline are included.

Thanks to the positive feedback minimizes time decision for a speci fi c power and area consumption, and therefore can increase the frequency conversion.

He, S, Zhan, D. Unfortunately, this architecture is quite sensitive to technological process, environmental conditions, as well as the mismatch between transistors and charge differences cf. I, S, Zhan, D. Geiger, "A simple and accurate method to predict offset voltage comparators in dynamic ", Proc. The great variability of comparators based on a single latch known as stand-alone latch limits its application to converters of very low accuracy, with typical resolutions of bits.

The problem of offset in the comparators has traditionally sought to reduce, regardless of the architecture of ADC considered, by employing techniques in the analog domain. In the publication, and P. The main disadvantage of this method, regardless of complexity, is causing an increase in load on internal knots which obviously moves to a degradation of dynamic performance. Another possibility commonly considered in the literature is the use of a preamp fi er to input latch, with or without phase cancellation itself offset see B.

Although this additional block attenuates the contribution to total LATCH offset its profit, introduces a considerable increase in total power consumption while increasing decision time reducing the maximum operating frequency. An alternative to overcome the limitations of the prior art in low senal digital pseudoaleatoria applications and high-speed calibration.

As detailed below, these methods can be classified into two groups depending on whether or compensation of the offset in the comparators not affect the natural path of the analog input signal. In the first group calibration techniques with non-concurrent phase measurement those procedures that break the driveway to inject a stimulus calibration senal digital pseudoaleatoria.

Baird, MM Kostelnik y M. In the publication, IR Nadi, R. Once the measurement phase comparators function is exchanged and starts a new calibration cycle. Senal digital pseudoaleatoria main disadvantage of this approach, regardless of the spurious caused by the periodic exchange of comparators, is the additional cost in hardware and power due to redundant hardware.

En las publicaciones, R. In this method the hardware duplication is avoided, occasionally removing a sample of the input signal, to substitute a DC stimulus allowing compensation of offset. To retrieve information lost senal digital pseudoaleatoria the calibration cycle, the digital logic interpolates sample recon fi guring omitted the remaining comparators. Apart from the complexity of the resulting logic, high sensitivity to frequency interpolation and limited effectiveness for high frequency signals, this technique requires periodic refresh calibration measurements since the offset value is stored, following a similar to that introduced in B.

During the measurement phase of this technique, the input senal digital pseudoaleatoria is interrupted to inject a DC stimulus, while a scan is performed on a digital ramp calibration code. This modi fi ed code by an additional digital-analog converter the authors suggest a capacitive embodiment thereof effective threshold voltage of the comparator.

The optimal value for the offset cancellation is selected independently monitoring the digital output of each comparator. Similar to the previous cases, to achieve a process of concurrent calibration virtual modethis technique will need either include additional hardware, resulting in power consumption and area, or omitting one of the input samples to include stimuli calibration with consequent degradation of performance due to interpolation.

This new senal digital pseudoaleatoria makes use of adaptive digital senal digital pseudoaleatoria procedures for indirect estimation of calibration codes, without duplication of devices and avoiding the problems associated with interpolation logic.

In the publication, Z. This method, based on the statistical properties of the system, digitally amending the threshold voltages of the comparators assuming a uniform distribution input signal.

The major drawback of this method is, as the authors acknowledge, not operating correctly when the input distribution uniform away from the nominal case. Thus in a generic situation with an arbitrary distribution, such as a sinusoidal input signal or input with Gaussian distribution, the adaptation process can lead to an offset and superior to the initial state uncalibrated nonlinearity.

The dependence of the calibration procedure in the particular input stimulus can be reduced by injecting a pseudorandom digital sequence in the system and subsequent correlation. The biggest disadvantage of this technique is that, being senal digital pseudoaleatoria correlation based method requires a fairly high convergence time.

This time is increased significantly when calibrating independently for each comparator, regardless ADC full information as the quantization error in this situation it is strongly correlated with the input. It is therefore considering the nomenclature introduced in the senal digital pseudoaleatoria section bibliographic ca, of an implementation of concurrent real-calibration. Obviously, the application senal digital pseudoaleatoria this procedure in not concurrent, but less interesting, is also a valid senal digital pseudoaleatoria.

The proposed adaptive method avoids the disadvantages of existing techniques of concurrent calibration, eliminating the need for redundant hardware, eliminating the problems associated with the logical interpolation, and ensuring a high rate of convergence against techniques based on correlation with pseudorandom numbers, all with some modifications insigni fi cant in the standard topology ADCUC.

As a result, they will be able to relax the specifications of precision in the design of the comparators, thus allowing an optimized in terms of power and speed design. Although the invention is completely general and can be applied to a generic topology comparator with or without preamp fi er direct comparators type application standalone latch in CMOS processes will allow: The following terms and notations used herein are introduced.

As its name suggests, an analog-digital converter is a system that translates the analog value of a certain signal xa to a digital representation. The code resulting output c is encoded, as shown in Fig. In practice, the second order effects in the system, as the random mismatch between components, gain errors and offset, and, dependent variations of temperature changes and polarization introduce a deviation from the nominal behavior can degrade the performance of the ADC.

Como se muestra en la Fig. Therefore, the INL is known uniquely determined offset in the analog comparators. Summarizing the notation and terms used throughout the document emphasize that: This measurement or estimate of the current actual transitions Ti can senal digital pseudoaleatoria performed concurrently any that may exist in the senal digital pseudoaleatoria, although subsequently described herein senal digital pseudoaleatoria preferred method.

It is understood that given the existing logical relationship between INLI, digital estimate of Ti transition and offset OFFi digital representation of the comparator is only necessary to know one of these values, with an irrelevant choice in the process. Each digital calibration code Ki adaptively moves the transition from low associated calibration comparator Compi to cancel the existing offset.

Although, as already mentioned, the invention is completely general and can be applied to a generic architecture comparator with or without preamp fi er, in the particular case of a latch regenerative comparator type, the correction term is introduced considering a bank of programmable transistors controlled the digital signal Ki amending the impedance at some of the internal nodes of senal digital pseudoaleatoria comparator.

The implementation considered, regardless of a mismatch fi xed for generating the default threshold, a bank of programmable transistors. Other implementations of programmable comparator valid for the invention may be based, as in K.

En caso In case. Obviously, it is irrelevant the order in which these comparisons, which could also be performed in parallel are made. In summary, the process of the invention requires initially zero calibration codes Ki.

Then the following operations are performed: Depending on the result of this comparison, the following actions are performed: These properties will allow, as discussed in practical embodiments of the invention for systems mixed signal over an ADC fl ash is its topology such senal digital pseudoaleatoria ADC Pipeline typeperforming compensation senal digital pseudoaleatoria the offset in several ADCs simultaneously, without cause harmful interference between them.

Obviously, the ADCs under calibration ADCUCs can be calibrated also sequentially, in which case they may refuse some or all calibration hardware resources. To ensure a monotonous behavior, in this situation, a coding thermometric-binary er is used Senal digital pseudoaleatoria to Binary Codi fi er, TBC, according to its acronym in Englishwhich performs the sum or account of a the thermometer code senal digital pseudoaleatoria by the comparators, regardless of the relative position therebetween.

The offset calibration using an senal digital pseudoaleatoria based TBC is performed without considering the specific relationship between a fi ca particular comparator and associated transition, since this information is eliminated in senal digital pseudoaleatoria process of each account. Consequently each comparator Compi has associated a priori transition fi ti ha for which the calibration code regardless of existing offset error is updated.

In any other situation, the output bits remain unchanged. Another possible implementation to reorder the transitions considered a small memory. Regardless of the number of low ADCUC calibration, and as previously mentioned herein, Tj obtaining digital estimate of the current position of transitions you a ADCUC can be performed in different ways.

In a preferred embodiment of the invention, this estimation is performed by a second adaptive process. This second estimation procedure initializes transitions, as detailed in the flow diagram simplified ed in FIG. Note that similarly to the calibration procedure of the invention estimates the digital transitions can actualizase using a constant adaptive step, but also be possible to senal digital pseudoaleatoria a process in senal digital pseudoaleatoria the steps were variables.

Finally, the current value of transitions Ti is transmitted to the following method steps for generating codes corresponding calibration. It is understood, as we have previously discussed senal digital pseudoaleatoria the document, given the existing logical relationship between INLI, digital estimate of Ti transition, andthe OFFi digital representation of the offset in the comparator, any of these estimates or derived therefrom are valid for the calibration procedure.

Choosing one of these estimates is irrelevant. There are different ways to implement this second estimation senal digital pseudoaleatoria. For example, the digital estimate X of the analog input x can be performed, as shown in the generic mixed system of Fig. Note that this additional converter may be low cost in power and area, as: Likewise, senal digital pseudoaleatoria is possible to control senal digital pseudoaleatoria conversion cycle adctest by a pseudorandom number generator senal digital pseudoaleatoria by a simple feedback shift register.

Furthermore, in systems where there is available for building a digital estimate X of the analog input signal xthe implementation of the estimation procedure is performed at minimum senal digital pseudoaleatoria in the analog domain as it is not required the adctest. This senal digital pseudoaleatoria consists of multiple stages STGseach of which has a sub-ADC of type fl ash capable of being calibrated with the invention with a low cost, either simultaneously or sequentially with or without refuse hardware calibration.

Obviously, if senal digital pseudoaleatoria you can make a truncation of the resulting digital signal X to downsize word. A second aspect of the present invention is directed to a logical unit of concurrent offset calibration comparators of an analog-digital converter ADC type fl ash, which performs the calibration procedure described above, comprising the following elements: A preferred embodiment of the logic unit calibration of the invention further comprises means for digital offset estimation ADC comparators, or equivalently effective transitions associated Ti.

Senal digital pseudoaleatoria caso de seleccionar las transiciones como variables del proceso, estos medios comprenden: If select transitions as process variables, these means comprise: To senal digital pseudoaleatoria the description being made and in order to aid a better understanding of the characteristics of the senal digital pseudoaleatoria, according to a preferred practical embodiment thereof, accompanying as an integral senal digital pseudoaleatoria of said description, a set of drawings where illustration and not limitation, is shown as follows: Characteristic input-output of an ideal r-bits with details of the definitions of transitions tj ADC.

Implementation CMOS for low voltage comparator with digital control transitions considering a bank of transistors or programmable varactors in parallel branches sensing the input signal unreferenced external comparison. Diagram of the digital flow measuring method for concurrent estimation of effective transitions comparators with digital serial comparison.

Feature input-output stage for a 2-bit transitions with deviations due to offset in the comparators, illustrating its impact on the output range OS of the MDAC amplifier. Fig 14 input-output characteristics of sub-ADC1 and STG1 in the case study 1 of example 2 with violation of redundancy. A before and b after the adaptive offset calibration.

A before and b after the adaptive calibration offset in the first two stages. Fig 16 Evolution of transient adaptive calibration measurements for one of the comparators of the senal digital pseudoaleatoria in the case study 1 of example 2 with violation of redundancy: Transfer function of the first stage under calibration senal digital pseudoaleatoria the case study 2 of Example 2 no violation of redundancy senal digital pseudoaleatoria detail spectrum final output.

Subsequently described in greater detail the embodiment of the invention in the particular case of the converter, or converters, type fl ash under calibration is part of a Pipeline ADC higher resolution.

Implementation of senal digital pseudoaleatoria estimation senal digital pseudoaleatoria calibration of this second case are directly extrapolated to the first case. Ejemplo 1 Example 1. The system consists of:

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The object of the present invention is a process for offset calibration comparators analog to digital converters ADCs. Application to a direct conversion topology known as flash type ADC allows the concurrent calibration Ia nonlinearity due to said offset.

Among these architectures the sigma-delta topologies, subranging, interpolation of successive approximations, interleaved and multi-stage also known as Pipeline are included. Thanks to positive feedback is minimized Ia decision time for a specific area and power consumption, and therefore can increase the frequency conversion. Unfortunately, this architecture is quite sensitive to technological process, environmental conditions, as well as the mismatch between transistors and differences loads Ia J.

I, S, Zhan, D. Geiger, "A simple and accurate method to predict offset voltage comparators in dynamic, "Proc. The great variability of comparators based on a single latch known as stand-alone latch limits its application to converters of very low accuracy, with typical resolutions of bits. The problem of offset in the comparators has traditionally sought to reduce, regardless of the architecture of ADC considered, by employing techniques in the analog domain.

In the publication, and P. The main disadvantage of this method, regardless of the complexity is causing an increase in the load on the internal knots which obviously moves to a degradation of dynamic performance.

Another possibility commonly considered in Ia literature is the use of a preamplifier to the input of the latch, with or without phase cancellation of own offset see B. Although this additional block attenuates Ia contribution to total LATCH offset its profit, introduces a considerable increase in total power consumption while increasing decision time Ia reducing maximum frequency of operation. An alternative to overcome the limitations of the prior art in low power applications and high speed is the calibration.

As detailed below, these methods can be classified into two groups depending on whether or Ia offset compensation in comparators not affect the natural path of Ia input analog signal. In the first group calibration techniques with non-concurrent phase measurement those procedures that break the driveway to inject a stimulus calibration included.

In the publication, IR Nadi, R. Once completed the phase measuring the function of the comparators is exchanged and starts a new calibration cycle. The main disadvantage of this approach, regardless of the spurious caused by the periodic exchange of comparators, is the additional cost in hardware and power due to redundant hardware. In this method Ia hardware duplication is avoided, occasionally removing a sample of the input signal, to substitute a DC stimulus allowing compensation of offset.

For recovering the lost information during the calibration cycle, Ia digital logic performs an interpolation of the sample omitted reconfiguring the remaining comparators. Regardless of the complexity of Ia resulting logic, Ia great sensitivity to the frequency interpolation and Ia limited effectiveness for high frequency signals, this technique requires periodic refresh calibration measurements since the offset value is stored, following a similar to the method introduced in B.

During the phase measurement this technique, the conversion input is interrupted for injecting a DC stimulus, while a scan is performed on a digital ramp calibration code. This code modified by a digital to analog converter further the authors suggest a capacitive embodiment thereof the voltage effective comparator threshold.

The optimal value for the offset cancellation Ia is selected independently monitoring the digital output of each comparator. Similar to the previous cases, to achieve a process of concurrent calibration virtual mode , this technique will need either include additional hardware, resulting in power consumption and area, or omitting one of the input samples to include stimuli calibration with the consequent degradation of performance due to the interpolation.

This new approach makes use of adaptive digital low-cost procedures for indirect estimation of calibration codes, without duplication of devices and avoiding the problems associated to the interpolation logic. In the publication, Z. This method, based on the statistical properties of the system, digitally modifies the threshold voltages of the comparators assuming a uniform distribution the input signal. The major drawback of this method is, as the authors acknowledge, not operating correctly when the distribution input away from the uniform nominal case.

Thus in a generic situation with an arbitrary distribution, such as a sinusoidal input signal or input with Gaussian distribution, the adaptation process can lead to an offset and superior to the initial state uncalibrated nonlinearity. The dependence of the calibration procedure in the particular input stimulus can be reduced by the injection of a pseudo-random digital sequence in the system and subsequent correlation. The biggest disadvantage of this technique is that, being a correlation based method requires a fairly high convergence time.

This time is increased significantly when performing the calibration independently for each comparator, regardless of the information of the complete ADC, since the quantization error in this situation is strongly correlated with the input.

It is therefore serving Ia nomenclature introduced in the section of literature review of an implementation of concurrent real-calibration. Obviously, the application of this procedure in non-concurrent, though less interesting, is also a valid solution.

The proposed adaptive method avoids the disadvantages of existing techniques of concurrent calibration eliminated Ia need for redundant hardware, eliminating the problems associated to the interpolation logic, and ensuring a high rate of convergence against techniques based on correlation with pseudorandom numbers, all with a few minor modifications to standard topology ADCUC Ia.

As a result, they will be able to relax the accuracy specifications in the design of the comparators, thus allowing an optimized in terms of power and speed design. Although the invention is completely general and can be applied to a generic topology comparator with or without preamplifier, direct application to comparators type stand-alone latch in CMOS processes will allow: The following terms and notations used herein are introduced.

As its name suggests, a digital analogue converter is a system that translates the analog value of a certain signal xa to a digital representation. The resulting output code c is encoded as is shown in Fig. In Ia practice, the second order effects in the system, as the random mismatch between components, gain errors and offset, and, dependent variations of changes in the temperature and polarization, introduce a deviation from the nominal behavior can degrade the performance of the ADC.

As shown in Fig. Should be noted that in the particular case of a flash type ADC of the measurement of the INL is directly related to the effective offset in the analog comparators of the ADC, in the shape,. Therefore, known Ia INL is uniquely determined offset in the analog comparators.

As a summary of Ia notation and terms used along the length of the document emphasize that:. The signal c defines the exit code ADCUC, which generally will be affected by errors nonlinearity caused mimo, according to equation 3 , the effective offset in their comparators. The variable resolution N uppercase X represents a digital estimate Ia analog input x with greater precision than the output code of ADCUC previously defined by c. The integer n is the index update procedure. Unless strictly necessary, this variable is implicitly assumed to simplify notation Ia.

Io following, we distinguish the index j, Ia transition? The calibration procedure of the invention requires as starting data besides the code output c of ADCUC, a digital representation X of greater precision than c of Ia input analog signal x and a digital estimate T 1 ADCUC current transitions associated with each comparator Comp, ,.

This measurement or estimate of the current actual transitions T 1 can be made of any concurrently Ia that may exist in literature although later described herein a preferred method. It is understood that given Ia existing logical relationship between INL ,, the digital estimate Ia transition T 1 and the digital representation OFF, the offset in the comparator, is only necessary to know one of these values, with an irrelevant choice in the process.

Although, as already mentioned, the invention is completely general and can be applied to a generic architecture comparator with or without preamplifier, in the particular case of a latch regenerative comparator type, the correction term is introduced considering a bank of programmable transistors controlled the digital signal by K 1 which modifies the impedance at some of the internal nodes of the comparator.

The implementation considered, apart from a fixed mismatch for generating the default threshold, a bank of programmable transistors. Other implementations of programmable comparator valid for the invention may be based, as in K.

Obviously, it is irrelevant the order in which these comparisons, which could also be performed in parallel are made. In summary, the method of the invention requires initially zero calibration codes K 1. Then the following operations are performed:. It is also considered irrelevant variable change in the calibration code K1 consistent with the programmable comparator keep Ia negative feedback loop. These properties will allow, as discussed in practical embodiments of the invention for systems mixed signal with more than one ADC flash is its topology such as ADC Pipeline type , perform Ia compensation offset in several ADCs simultaneously, without cause harmful interference between them.

Obviously, the ADCs under calibration ADCUCs can be calibrated also sequentially, in which case you can reuse some or all calibration hardware resources.

To ensure a monotonous behavior, in this situation, a thermometric-binary encoder is used Thermometer to Binary codifier, TBC, according to its acronym in English , which performs the sum or account of a the thermometer code provided by the comparators, regardless of the relative position therebetween.

The offset calibration using an adder based TBC is performed without considering Ia specific relationship between a particular comparator and associated transition, since this information is eliminated in the process of each account.

Consequently each comparator Comp is associated a priori fixed transition t, with respect to the calibration code which independently existing offset error is updated. In any other situation, the output bits remain unchanged. Another possible implementation to reorder the transitions considered a small memory. In a preferred embodiment of the invention, this estimation is performed by a second adaptive process.

This second estimation procedure initializes transitions, as detailed in the simplified flow chart of Fig. Note that similarly to the calibration procedure of the invention estimates the digital transitions can actualizase using a constant adaptive step, but also be possible to design a process in which the steps were variables.

Finally, the current value of the transitions T 1 is transmitted to the following method steps for generating codes corresponding calibration. It is understood, as we have previously discussed in the document, given Ia existing logical relationship between INL ,, the digital estimate Ia transition T, and the digital representation OFF, the offset in the comparator, any of these estimates or derived from these are valid for the calibration procedure. Choosing one of these estimates is irrelevant.

There are different ways to implement this second estimation procedure. For example, the digital estimate X of the analog input x can be performed, as shown in the system of the generic mixed Fig. Note that this additional converter may be low cost in power and area, as: Likewise, there is the possibility of controlling the conversion cycle adctest by a pseudorandom number generator made by a simple feedback shift register. This converter consists of multiple stages STGs , each of which has a sub-ADC type capable of being calibrated with the invention at a low cost, either simultaneously or sequentially with or without reuse hardware flash calibration.

Obviously, if desired you can make a truncation of the digital signal resulting X to downsize word. A second aspect of the present invention is directed to a logical unit of concurrent offset calibration comparators of an analog-digital converter ADC flash type, which performs the calibration procedure described above, comprising the following elements:.

A preferred embodiment of the calibration logic unit of the invention further comprises means for the digital offset estimation ADC comparators, or equivalently effective Ia transitions associated T 1. If select transitions as process variables, these means comprise:. To complement the description being made and in order to aid a better understanding of the characteristics of the invention, according to a preferred practical embodiment thereof, accompanying as an integral part of said description, a set of drawings in an illustrative and non-limiting character it is represented:.

Characteristic input-output of an ideal r-bits with details of the definitions of transitions tl ADC. Implementation CMOS for low voltage comparator with digital control transitions considering a bank of transistors or programmable varactors in parallel branches sensing the input signal unreferenced external comparison.

Flowchart digital measurement procedure for Ia concurrent estimation of effective transitions comparators with digital serial comparison. Simplified of the preferred embodiment for the calibration of the offset comparators in flash ADC type diagram. Feature input-output stage for a 2-bit transitions with deviations due to offset in the comparators, illustrating its impact on the output range OS MDAC amplifier.

A before and b after the adaptive offset calibration. A before and b after the adaptive calibration offset in the first two stages. Fig 16 Evolution of transient adaptive calibration measurements for one of the comparators of the stages in the case study 1 of example 2 with violation of Ia redundancy: Without offset calibration; b calibrating the offset nonlinear amplifier with reduced output range.

Transfer function of the first stage under calibration in the case study 2 of Example 2 no violation of redundancy Ia showing the final output spectrum. Subsequently described in greater detail the embodiment of the invention in the particular case of the converter, or converters, flash type under calibration is part of a Pipeline ADC higher resolution. Ia implementing logic estimation and calibration of this second case are directly extrasolar the first case.

The system consists of:. As already discussed, this converter can operate at a lower frequency to that of the ADCUC allowing relaxing the specifications of power and area thereof.